The source of speed limitations in conventional space switch arrays is illustrated by considering a K.times.J matrix including K inputs each of which can be connected to the J outputs by closing the switch at the intersection of an input/output line. The switches have associated stray capacitances that cause speed degradation. Therefore, the speed decreases as the size of the array is increased. For example, by closing a switch S11 at the intersection of row 1 and column 1, input 1 is connected to output 1. Even though inputs 2 to K are not connected, they contribute to the stray capacitance of column 1. Similarly, even though columns 2 to J are not connected, they contribute to the stray capacitance of row 1. It can be seen that input line 1 must charge (J-1)+(K-1) capacitors. The finite resistance in series with line 1 and column 1 forms an RC time constant that limits the speed of operation. As the array size is increased, this stray capacitance also increases and the speed continues to decrease.
The stray capacitance of the horizontal rows can be overcome by providing sufficient drive to the input lines. The most detrimental effect is caused by connections to the vertical lines. This is due to the fact that each of the switches at the crosspoints is implemented with an active circuit that must drive the vertical line and its associated capacitive loading. It does not help to make the active switch element larger so it can drive more capacitance because the stray capacitance increases in almost direct proportion to the size of the active switch.